#ifndef __FH_I2C_H
#define __FH_I2C_H

#define FH_IC_CON		0x0
#define FH_IC_TAR		0x4
#define FH_IC_SAR		0x8
#define FH_IC_DATA_CMD		0x10
#define FH_IC_SS_SCL_HCNT	0x14
#define FH_IC_SS_SCL_LCNT	0x18
#define FH_IC_FS_SCL_HCNT	0x1c
#define FH_IC_FS_SCL_LCNT	0x20
#define FH_IC_INTR_STAT		0x2c
#define FH_IC_INTR_MASK		0x30
#define FH_IC_RAW_INTR_STAT	0x34
#define FH_IC_RX_TL		0x38
#define FH_IC_TX_TL		0x3c
#define FH_IC_CLR_INTR		0x40
#define FH_IC_CLR_RX_UNDER	0x44
#define FH_IC_CLR_RX_OVER	0x48
#define FH_IC_CLR_TX_OVER	0x4c
#define FH_IC_CLR_RD_REQ	0x50
#define FH_IC_CLR_TX_ABRT	0x54
#define FH_IC_CLR_RX_DONE	0x58
#define FH_IC_CLR_ACTIVITY	0x5c
#define FH_IC_CLR_STOP_DET	0x60
#define FH_IC_CLR_START_DET	0x64
#define FH_IC_CLR_GEN_CALL	0x68
#define FH_IC_ENABLE		0x6c
#define FH_IC_STATUS		0x70
#define FH_IC_TXFLR		0x74
#define FH_IC_RXFLR		0x78
#define FH_IC_COMP_PARAM_1	0xf4
#define FH_IC_TX_ABRT_SOURCE	0x80
#define FH_IC_ENABLE_STATUS 0x9c

#define FH_IC_CON_MASTER		0x1
#define FH_IC_CON_SPEED_STD		0x2
#define FH_IC_CON_SPEED_FAST		0x4
#define FH_IC_CON_10BITADDR_MASTER	0x10
#define FH_IC_CON_RESTART_EN		0x20
#define FH_IC_CON_SLAVE_DISABLE		0x40

#define FH_IC_INTR_NONE         0x0
#define FH_IC_INTR_RX_UNDER	0x001
#define FH_IC_INTR_RX_OVER	0x002
#define FH_IC_INTR_RX_FULL	0x004
#define FH_IC_INTR_TX_OVER	0x008
#define FH_IC_INTR_TX_EMPTY	0x010
#define FH_IC_INTR_RD_REQ	0x020
#define FH_IC_INTR_TX_ABRT	0x040
#define FH_IC_INTR_RX_DONE	0x080
#define FH_IC_INTR_ACTIVITY	0x100
#define FH_IC_INTR_STOP_DET	0x200
#define FH_IC_INTR_START_DET	0x400
#define FH_IC_INTR_GEN_CALL	0x800

#define FH_IC_INTR_DEFAULT_MASK		(FH_IC_INTR_RX_FULL | \
					 FH_IC_INTR_TX_EMPTY | \
					 FH_IC_INTR_TX_ABRT | \
					 FH_IC_INTR_STOP_DET)

#define MAX_CHAR_NUM		20

/* i2c enable register definitions */
#define IC_ENABLE_0B		0x0001

/* Speed Selection */
#define I2C_SPEED_FAST  400000
#define I2C_SPEED_STANDARD	100000
#define IC_SPEED_MODE_STANDARD 1
#define IC_SPEED_MODE_FAST  2

/* i2c control register definitions */
#define IC_CON_SD		0x0040
#define IC_CON_RE		0x0020
#define IC_CON_10BITADDRMASTER	0x0010
#define IC_CON_10BITADDR_SLAVE	0x0008
#define IC_CON_SPD_MSK		0x0006
#define IC_CON_SPD_SS		0x0002
#define IC_CON_SPD_FS		0x0004
#define IC_CON_SPD_HS		0x0006
#define IC_CON_MM		0x0001

/* i2c interrupt status register definitions */
#define IC_GEN_CALL		0x0800
#define IC_START_DET		0x0400
#define IC_STOP_DET		0x0200
#define IC_ACTIVITY		0x0100
#define IC_RX_DONE		0x0080
#define IC_TX_ABRT		0x0040
#define IC_RD_REQ		0x0020
#define IC_TX_EMPTY		0x0010
#define IC_TX_OVER		0x0008
#define IC_RX_FULL		0x0004
#define IC_RX_OVER 		0x0002
#define IC_RX_UNDER		0x0001

/* fifo threshold register definitions */
#define IC_TL0			0x00
#define IC_TL1			0x01
#define IC_TL2			0x02
#define IC_TL3			0x03
#define IC_TL4			0x04
#define IC_TL5			0x05
#define IC_TL6			0x06
#define IC_TL7			0x07
#define IC_RX_TL		IC_TL0
#define IC_TX_TL		IC_TL0

/* i2c status register  definitions */
#define IC_STATUS_SA		0x0040
#define IC_STATUS_MA		0x0020
#define IC_STATUS_RFF		0x0010
#define IC_STATUS_RFNE		0x0008
#define IC_STATUS_TFE		0x0004
#define IC_STATUS_TFNF		0x0002
#define IC_STATUS_ACT		0x0001

/* i2c data buffer and command register definitions */
#define IC_CMD			0x0100
#define IC_STOP			0x0200


#define I2c_DisEnable(base_addr)  writel(0, base_addr + FH_IC_ENABLE)
#define I2c_Enable(base_addr)  writel(1, base_addr + FH_IC_ENABLE)
#define I2c_Enable_Status(base_addr) readl(base_addr + FH_IC_ENABLE_STATUS)
#define I2c_SetCon(base_addr, config)  writel(config, base_addr + FH_IC_CON)
#define I2c_GetCon(base_addr)      readl(base_addr + FH_IC_CON)
#define I2c_SetIntrMask(base_addr, mask)   writel(mask,\
		base_addr + FH_IC_INTR_MASK)

#define I2c_SetTxRxTl(base_addr, txtl, rxtl)    do {\
	writel(txtl, base_addr + FH_IC_TX_TL);   \
	writel(rxtl, base_addr + FH_IC_RX_TL);   \
	} while (0)

#define I2c_SetSsHcnt(base_addr, hcnt)  writel(hcnt,\
		base_addr + FH_IC_SS_SCL_HCNT)
#define I2c_SetSsLcnt(base_addr, lcnt)  writel(lcnt,\
		base_addr + FH_IC_SS_SCL_LCNT)
#define I2c_SetFsHcnt(base_addr, hcnt)  writel(hcnt,\
		base_addr + FH_IC_FS_SCL_HCNT)
#define I2c_SetFsLcnt(base_addr, lcnt)  writel(lcnt,\
		base_addr + FH_IC_FS_SCL_LCNT)
#define I2c_SetDeviceId(base_addr, deviceID)   writel(deviceID,\
		base_addr + FH_IC_TAR)  /* set IIC  slave address */
#define I2c_Status(base_addr)     readl(base_addr + FH_IC_STATUS)
#define I2c_Write(base_addr, data)  writel(data, base_addr + FH_IC_DATA_CMD)
#define I2c_Read(base_addr)   (readl(base_addr + FH_IC_DATA_CMD)&0xff)
#define I2c_SetIntrMask(base_addr, mask)   writel(mask,\
		base_addr + FH_IC_INTR_MASK)
#define I2C_GetIntrStat(base_addr)  readl(base_addr + FH_IC_INTR_STAT)
#define I2C_GetTransmitFifoLevel(base_addr)   (readl(base_addr + \
		FH_IC_TXFLR))
#define I2c_ClrIntr(base_addr, mask)   readl(base_addr + mask)

#if !defined(IC_CLK)
#define IC_CLK		50000000
#endif

#define I2C_WAIT_TIME		50

struct fh_i2c {
	unsigned int base;
};

#endif